1. Field of the Invention
The present invention relates to a semiconductor device enhanced in the speed of switching from an ON state to an OFF state, and to a method of driving the same.
2. Description of the Related Art
A memory (especially for application to SRAM) in which thyristors are used, the turn-on/turn-off characteristics of the thyristors are controlled by gate electrodes realized on the thyristors, and the thyristors are connected in series with access transistors, has been proposed (the memory will hereinafter be referred to as T-RAM). The T-RAM performs memory actions with the OFF region of the thyristor as “0” and the ON region as “1”.
The thyristor has a basic structure in which a p-type region p1, an n-type region n1, a p-type region p2, and an n-type region n2 are junctioned in order, and in which n-type silicon and p-type silicon are used in a total of four layers. This basic structure will hereinafter be expressed as “p1/n1/p2/n2”. Two kinds of configurations have been proposed by T-RAM. One has the p1/n1/p2/n2 structure vertically built up on a silicon substrate, and the other has the p1/n1/p2/n2 structure arranged laterally in a silicon layer by using a SOI substrate. In either of the configurations, a gate electrode with a MOS structure is provided over p2 of the p1/n1/p2/n2, thereby permitting high-speed operation.
For example, as shown in FIG. 18A, the semiconductor device with the thyristor configuration has a first p-type region p1, a first n-type region n1, a second p-type region p2, and a second n-type region n2 which are Functioned in order, thereby forming the p1/n1/p2/n2 structure. An anode A is connected to the first p-type region p1 on one end side, and a cathode K is connected to the second n-type region n2 on the other end side. Further, a gate electrode G is arranged at the second p-type region p2 disposed on the inside. Such a thyristor has either of a configuration in which the p1/n1/p2/n2 structure is vertically arranged in a surface layer of a silicon substrate and a configuration in which the p1/n1/p2/n2 structure is laterally arranged by use of a SOI substrate.
In the semiconductor device with the thyristor configuration, when a forward bias is impressed between the anode A and the cathode K as shown in FIG. 18B, holes are supplied from the p-type region p1 connected to the anode A into the n-type region n1, and electrons are supplied from the n-type region n2 connected to the cathode K into the p-type region p2. Then, the holes and electrons are recombined in a junction portion between the n-type region n1 and the p-type region p2, whereby a current is permitted to flow, and an ON state is obtained.
On the other hand, when a reverse bias is impressed between the anode A and the cathode K as shown in FIG. 18C, an OFF state is obtained; however, it takes a time of a few microseconds (ms) to obtain a substantial OFF state. In other words, once the ON state is attained, spontaneous switching from the ON state to the OFF state would not occur when a reverse bias is simply impressed between the anode A and the cathode K. It is only after the current is reduced to below a holding current or the power source is turned off that the excess carriers flowing in the n-type region n1 and the p-type region p2 can entirely be swept out of these regions or be recombined.
Therefore, while a negative voltage is impressed on the anode A and a positive voltage is impressed on the cathode K to establish a reverse-biased condition at the time of switching from the ON state to the OFF state, if this operation is conducted alone, it would take a few microseconds (ms) to achieve the intended switching. In practice, therefore, a voltage is impressed on the gate electrode (thyristor gate) provided at the p-type region p2 as shown in a pulse timing chart in FIG. 19, whereby an electric field is generated in the p-type region p2 to forcibly discharge the electrons present as the excess carriers, thereby achieving a faster switching to a substantial OFF state. In this case, a high-speed operation on the order of a few nanoseconds (ns) is achieved.
In addition, there is a configuration called GTO (Gate Turn off Thyristor) in which a gate electrode is in direct contact with the p-type region p2. The configuration in which a MOS electrode is provided is a modified example of the GTO, and the role of the electrode is the same as above.
Meanwhile, at the time of turning-off operation, i.e., “write 0” operation in the case of a cell array, a voltage for a reverse bias condition is simultaneously applied from the cathodes to the cells on the same bit line as the selected bit, but no voltage is impressed on the thyristor gates of non-selected bits. Therefore, the turn-off speed of the non-selected bits is so slow that only the selected bit can be turned OFF.
In the case where a bulk silicon wafer is used, however, the p-type region p2 extends deep in the depth direction of the substrate, so that the bias impressed through the gate electrode ranges to only part of the p2 layer and, therefore, the effect of the impressing of the bias through the gate electrode would be limited.
In the next place, the relationship of the voltage (VAK) between the anode A and the cathode K in the semiconductor device having the thyristor configuration with the current (I) flowing in the semiconductor device will be described below, referring to FIG. 20.
As shown in FIG. 20, as a positive voltage is impressed on the anode A, the pn junction between the n-type region n1 and the p-type region p2 is forward-biased when the voltage VAK reaches a critical voltage VFB, whereon the voltage VAK is lowered and a current of not less than the holding current IH begins to flow. It is to be noted here, however, that only a switching current IS lower than the holding current IH flows until the voltage VAK reaches or exceeds the critical voltage VFB, and that a current greater than the holding current IH begins to flow when the voltage VAK has exceeded the critical voltage VFB.
A configuration with a MOS structure in which a gate electrode is disposed over the p-type region p2 through an insulating film therebetween so as to fasten the switching operation as above-mentioned has been proposed (refer to, for example, U.S. Pat. No. 6,462,359 (B1), Non-patent Document Farid Nemati and James D. Plummer, “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device”, 1998 IEEE, VLSI Technology Tech. Dig., p. 66, 19981, Non-patent Document Farid Nemati and James D. Plummer, “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories”, 1999 IEEE IEDM Tech., p. 283, 1999, and Non-patent Document Farid Nemati, Hyn-Jin Cho, Scott Robins, Rajesh Gupta, Marc Tarabbia, Kevin J. Yang, Dennis Hayes, Vasudevan Gopalakrishnan, “Fully Planar 0.562 μm2 T-RAM Cell in a 130 nm SOI CMOS Logic Technology for High-Density High-Performance SRAMs”, 2004 IEEE IEDM Tech., p. 273, 2004).